1. Field of the Invention
The present invention relates to a processor and an interrupt controlling method capable of processing a plurality of tasks or handling a plurality of interrupt processes in parallel.
2. Description of the Related Art
These days, a multiprocessor system and a multithreaded processor (hereinafter generically referred to as “multiprocessors”) capable of processing, in parallel, a plurality of tasks or threads (uniformly referred to as tasks in this specification) by including a plurality of processors are being used in embedded devices and the like. In a conventional mobile device, processing has been performed by a single processor. An increase in the sophistication of mobile devices has complicated processing performed therein, which has become difficult for a single processor to perform.
If a multiprocessor performs processing, it needs to respond to occurrence of an interrupt process differently from a single processor. For example, there are conceivable a method in which one of a plurality of processors is designated in advance as a processor which is to perform processing according to the type of interrupt and a method in which an interrupt signal is input to all of a plurality of processors, and arbitration among the processors is performed.
Note that techniques pertaining to a method for performing arbitration between processors in a multiprocessor to assign an interrupt process are described in JP-A-6-324996 (hereinafter referred to as Patent Document 1) and JP-A-2005-4562 (hereinafter referred to as Patent Document 2).
Each of the techniques described in Patent Documents 1 and 2 is a technique in which an interrupt controller is provided for each of processors in a multiprocessor, and arbitration between the interrupt controllers is performed upon occurrence of an interrupt request.
However, since an interrupt controller is provided for each processor in the technique described in Patent Document 1, pieces of hardware required become larger, and wiring becomes complicated. Accordingly, the technique is not suitable for embedded devices. If one of the plurality of processors is designated in advance as a processor which is to perform processing according to the type of interrupt as described above, a situation may arise in which an interrupt process is not executed even with a processor in a non-operating state. This may decrease processing efficiency.
It is difficult to efficiently handle processes with high priorities including an interrupt process in an environment with limited hardware resources, such as one in which a multiprocessor applied to an embedded device is placed. If interrupt control is performed mainly by software to suppress an increase in the size of hardware, it is disadvantageous in that the time required to select a processor and a delay in processing caused by an interrupt request are longer than when interrupt control is performed by hardware.
The conventional technique described in Patent Document 2 has been made with a focus on the fact that the priorities of interrupt processes are generally high. For this reason, requested interrupt processes are all accepted to prevent a request for an interrupt process from being made to wait by a process already being executed. Each of the accepted interrupt processes is assigned to one of the plurality of processors which is executing a process with the lowest priority.
In a multiprocessor, a processor may be disabled for interrupts to prevent a task being executed by the processor from being interrupted by another task or interrupt. However, according to the technique in Patent Document 2, since interrupt requests are all accepted, the meaning of disabling interrupts in a multiprocessor may be lost to affect operation.
Additionally, since the difference in priority between an interrupt process and a process being executed is not taken into consideration, there arises the problem of that a process being executed is interrupted by an interrupt even if the process has a particularly high priority.